Wide Range Neutron Flux Measuring Channel for Aerospace Application
R. M. Cibils\\ A. Busto\\ J.L. Gonella\\ R. Martinez^ A.J. Chielens\\ J.M. Otero\\ M. Nunez^ and S. E. Tropea^
'INVAP S.E., Moreno 1089, 8400 Bariloche, Rio Negro, ARGENTINA ^INTI, Av. Oral. Paz 5445, 1650 San Martin, Buenos Aires, ARGENTINA
'0054-2944-445400 0054-2944-448049 (fax), rcibils@invap.com.ar
Abstract. The use of classical techniques for neutron flux measurements in nuclear reactors involves the switching between several detection chains as the power grows up to 10 decades. In space applications where mass and size constraints are of key significance, such volume of hardware represents a clear disadvantage. Instead of requiring different instruments for each reactor operating range (start-up, ramping-up, and nominal power), a single instrument chain should be desirable. A Wide Range Neutron Detector (WRND) system, combining a classic pulse Counting Channel with a Campbell's theorem based Fluctuation Channel can be implemented for the monitoring and control of a space nuclear reactor. Such an instrument will allow for a reduction in the complexity of space-based nuclear instrumentation and control systems. In this presentation we will discuss the criteria and tradeoffs involved in the development of such a system. We will focus particularly on the characteristics of the System On Chip (SOC) and the DSP board used to implement this instrument.
Keywords: Space reactor instrumentation, wide range neutron flux measurements, signal processing electronics. PACS: 28,28.41.Rc, 28.41.My, 07.50.Qx.
INTRODUCTION
Although there is still too much information to be gathered about our solar system neighborhoods (Moon, Mars, Venus, Mercury), the farther planets are the ones that attract the most of our attention. In this field, the use of nuclear power for energy or even propulsion is beginning to be considered as the best alternative (Bennett, 2006). All the systems involved in space missions have to be not only highly reliable as usual in nuclear fields but also light in weight, small size and low power. In this sense, the classical technique to measure the power generated in the core of nuclear reactors, involving the switching between several detection chains as the power grows along up to 10 decades of neutron flux results inapplicable.
The combined use of pulse and fluctuation modes of a fission chamber is becoming a common practice for Wide Range Neutron Detection in terrestrial applications (Kropik, 2000). A Wide Range Neutron Detector (WRND) has been already developed, tested and installed at the OPAL (Open Pool Advanced Light - Water Reactor) in Australia (Gonella, 2004), being now full operative (see figs, la and lb). However, the analog signal processing section of this system presents several drawbacks in relation with its use in space due to signal drifts and components aging under radiation effects, especially when it is intended for long term missions. Digital systems equivalent to that are cited in the literature (Lescop, 2000), but just intended for terrestrial use. We present here the DSP electronics of a digital WRND, specifically designed to be used in neutron flux measurement for control and protection systems of a nuclear reactor in space missions.
SYSTEM
The WRND (Dc - 045 model) wide range "Campbellian" system is basically a fission detector (Nassif, E. et al, 2007) with adequate electronics, able to operate in pulse mode at low neutron flux and in current fluctuation mode at medium and high neutron fluxes. The electronic side of this system has been implemented using a triple redundant
CP969, Space Technology and Applications International Forum—STAIF 2008, edited by M. S. El-Genk © 2008 American Institute of Physics 978-0-7354-0486-l/08/$23.00
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(a) Electronic Modules.
(b) Fission Chamber.
FIGURE 1. WRND System Currently Being Installed at the Australian Research Reactor.
VME bus (see Figure 2) over which three identical units are mounted. Each unit is composed by an analog signal conditioning board, a Digital Signal Processor (DSP) board, a Single Board Computer (SBC), an I/O board and a 1553 Standard Communication board. The full system is composed by these three modules, a triple redundant power conditioning module, a Final Actuation Logic board and the fission detector.
Analog Board
This board contains a High Voltage Power Supply, a pulse shaping amplifier for the pulse region of the detector output and a wide band amplifier for the fluctuation region. Considering the low level of the signals involved in this board, a very careful grounding and shielding of all its areas is required. The design requires special attention to the input circuits and to the cable used to carry the signal from the detector output.
Triple Redundancy Architecture
Safety Interlocks
to Spacecraft Host
FIGURE 2. Block Diagram of the WRND System.
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CPU Board
This board is a high performance, low power and fault tolerance single board computer for space applications based on SPARC chip ATMEL TSC-695F. The board is capable of standard VME interfacing with master features.
DSP Board - Functional Description
The WRND operates taking advantage of two of the three modes of operation of the fission chamber. This chamber produces pulses with a count rate proportional to the neutron flux, in the lowest zone of the neutron flux measurement range. Above this zone, the pulses begin to "pile up" and a random fluctuation type of signal comes out of the fission chamber. This is called the fluctuation operation mode of this detector also called Campbell mode.
Campbell (Campbell and Francis, 1946; DuBndge, 1967; Thomas and McBride, 1968; Knoll, 1992) demonstrated that there is a relation between the estimated statistical moments of this signal and the neutron flux. It is possible to obtain an estimation of the neutron flux using the first statistical moment (mean) but with high background gamma noise (Matatagui and Sabate Puignal, 1980). As the order of the moment is increased the influence of this noise decrease, but the statistical uncertainty get also increased. A good trade off (Baers et al, 1993) is the use of the second statistical moment (conventional variance).
With this DSP board, it is possible to obtain an accurate estimation up to the sixth decade of neutron flux using the pulse mode. Also, the variance of the signal becomes a reasonable measure of the flux above the fourth decade. This allows an almost two decade transition zone where a convenient switching of the data stream can be produced by automatic means.
Board Implementation
The WRND Digital Signal Processing Module is being implemented on a 6U format VME board using engineering versions of space qualified components. This board receives both, the amplified shaped Gaussian pulses related with the lowest decades of the reactor neutron flux and the fluctuation signal produced by the fission detector operating on its Campbellian region of operation. The block diagram of the board can be seen in Figure 3.
Campbell Channel Input
GAIN CONTROLLED AMPLIFIER
pulses
reactor variables
FIGURE 3. Block Diagram of the DSP Board.
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The fluctuation signal is filtered using a passive bandpass filter in order to suppress the cero and aliasing frequencies components and then transfer them to the A/D converter through a variable gain amplifier. This gain can be set digitally from a host computer to compensate from the calibration degradation of the system by the aging of the detector and the analog electronic components. The nuclear shaped Gaussian pulses are discriminated by energy and counted. The discriminator threshold can be digitally set from the host computer.
All the configuration parameters of the board can be modified from the SBC board by VME bus accesses. A serial RS422 communication channel is also provided. The signal processing on the board is carried out by a DSP System On Chip. The DSP SOC produces a digital reading of the reactor core neutron flux in logarithmic scale along with the rate of this flux for control purposes and a trip request signal for safety actions. Full range output from pulses and Campbellian channels can also be achieved.
Although the DSP SOC has been prototyped over two reprogrammable FPGA devices, its code has been written using a transportable - technology independent - style, opening the door for single chip implementation and making it possible the migration towards radiation tolerant devices with minimum engineering rework.
DSP SOC DESCRIPTION
The DSP SOC operation can be described by the flow diagram shown in fig 4. This operation is achieved through the contribution of two different operative areas: the Communication Section and the Processing Section in the following way:
JL
PULSE COUNTING
i
CAMPBELL SIGNAL PROCESSING
NEUTRON FLUX CALCULATION
LOGARITHM CALCULATION
RATE CALCULATION
STATUS REFRESH
3Z
FIGURE 4. Flow Diagram of the DSP Board Operation.
The Communication Section is involved on the functions of changing or monitoring configuration parameters and transfer log scale neutron flux and rate data from the Processing Section through the WBAVB Bridge to the serial RS422 port or VME bus driver. These functions are achieved through the use of specific commands originated on an external processing device. It also feeds two D/A converters to provide an analogue version of the log scale neutron flux and rate data stream outputs. The Processing Section is the responsible for polling the Pulses and Campbell front end modules, processing the raw data coming from them and finally evaluate if the flow and rate values determines the conditions needed to make a trip requirement.
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Reactor Variables
Fluctuation Range (FR) 2^ High Power (HP)
High Rate (HR)
AIDS, D/A CONV
CAMPBELL CHANNEL
20 MHz System Clock
SIGNAL PROCESSOR
8 bits Data Bus
^1 PULSE
I
n
DISCRIMINATOR
CP PORT
ir
COMMUNICATION PROCESSOR
So Ljj Q
trip\_request SERIAL DAC
FIGURE 5. Block Diagram of the DSP SOC.
Figure 5 shows the internal structure of the DSP SOC. Apart from the functional division in two sections, the SOC has been distributed physically between two different devices in order to allow its implementation on low density FPGAs with space heritage. The internal logic of these sections is implemented using a standard bus (WISHBONE) over which RTL level blocks (cores), written in VHDL language are integrated.
The need to use more than one FPGA to implement the processing logic, calls for special precautions in the design of the general clock network of the entire system.
Another consequence of the distribution of the logic in more than one device, is the need to use independent buses and with that, independent systems on each one of them. In order to allow communication between both systems the buses have to be interconnected by means of a WISHBONEAVISHBONE bridge.
We have chosen an implementation of the WISHBONE bus (Opencores) with the following characteristics: shared type, 8 bits data bus and 8 bits address bus. The operating frequency of the bus clock will be 20 MHz.
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Processing Section - Signal Processor
The processor reads the outputs of the Front End Pulse Channel Module and the Front End Campbell Channel Module. After that, both are scaled. Although their contributions are produced over different parts of the neutron flux range, there is an overlapping region between them. In order to prevent non-linear behavior in the system operation, the way in which both channels contribute to the flux value calculation is controlled by the algorithm showed in Figure 6.
FIGURE 6. Flow Diagram of the Data Stream Switching.
As it can be seen here, the Campbell Channel data is always taken as a reference. If its value is greater than VMAX (which is always in the upper part of the overlapping region) the only contribution to the calculation of the flux will be the Campbell channel. If the Campbell Channel data has a value below VMIN, the only contribution to the calculation of the flux will be the Pulse channel. In the case where the Campbell Channel data has values between VMAX and VMIN, the contribution of both channels will depend on the sign of the variation of the flux. The decimal logarithm of this data stream is calculated. The output data word will be 32 bits floating point. It becomes necessary to insert a low-pass filter between the logarithm calculation stage output and the rate calculation stage input, because of the noisy nature of the signal. The rate calculation block is also implemented as a digital filter.
Pulse Channel Front End This module counts the amount of rectangular pulses that comes from the pulse channel discriminator during a time interval called integration period. The module has two operation modes: the one period and the multi-period mode. The first one consists on a simple integration procedure that store its results directly on the Pulse Channel Front End output register. The second mode accumulates the partial outputs of a sequence of multiple integrations until a suitable result is achieved. The switch between both modes is determined by a control algorithm that minimizes the value of the statistical uncertainty in the final result. This module begins its integration every time the signal processor executes a polling operation over it. The integration finishes 1/256 seconds after that.
Campbell Channel Front End This block calculates the square average of 1024 samples from the filtered fluctuation signal. This module begins its integration every time the signal processor polls it and finish at less than 1/256 seconds after that. Once finished the calculation it store its result in an output register and wait for the next signal processor polling.
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Trip Logic
The processing section use the calculated results in combination with external processes status signals to determine predefined trip conditions. This produces a digital Boolean output that calls for trip when are fulfilled that conditions.
Communication Section
The communication Section checks periodically the Rx channel from the UART and internal registers from the VMEAVB Bridge, in order to verify the arrival of external commands and transfers neutron flux and rate data from the WBAVB Bridge PC Port, toward the analogue output ports (D/A converters).
Communication Processor
The Communication Processor acts as a communication master for the commands that come from the serial data port and the VMEAVB Bridge. Except for the periodical refresh of the analogue outputs and inspection of the UART Status Register and internal registers of the WBAVB Bridge, all the other functions of this master are conditioned to the commands coming from the local SBC or remote host computer.
INITIAL CONFIGURATION
X ] [ Scanning of Serial Port & VME/WB Bridge
T.
Refreshing of Analog & VME Outputs
PARAMETER READING
][
COMMAND DECODING
JL
PARAMETER WRITING
][
NEUTRON FLUX VALUES READING
FIGURE 7. Flow Diagram of the Communication Processor Operation.
Three different types of functions can be serviced by this processor: the change of configuration parameters, the reading of current parameters and the reading of neutron flux related data (see fig. 7).
UART
As in the case of the interface with the VME bus, the UART block is used to configure the board or monitor the processing results and the status of the logic. As the aim is to achieve a significant economy of the silicon area occupied in the FPGA, this block will be customized to operate with a fix communication configuration in parameters such as speed, parity, and word format.
VME/WB Bridge
The DSP board registers may be accessed from an external intelligence through the VME bus. This access is made possible by a VMEAVISHBONE bridge that withstands up to 16-bit-wide data words. This block may be used to configure the board or monitor the results of the processing and the status of the logic.
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Monitor and WB/WB Bridge A digital driver for two analog outputs corresponding to LOG and RATE signals will be provided, just for debugging purposes. The Processing and the Communication sections interact through the WBAVB Bridge Ports. This bridge has two ports.: CP Port and PC Port. Both of them are unidirectional. The CP Port allows the writing of configuration parameters from the Communication Section to the Processing Section while PC Port allows the reading of the Configuration Parameters and the transference of log scale neutron flux and rate data towards the processing section. Each port is basically a dual port RAM memory that can be written from one section and read from the other. The use of internal control logic in the RAM WISHBONE interfaces on input and output, and the microcontrollers wait state capability prevents the occurrence of metastability effects in the data transference between both sections.
RESULTS AND DESIGN TRADE OFFS
A prototype version of the DSP board was tested under real conditions in the RA6 reactor. This facility is a 500kW thermal power reactor for research and training that was built by INVAP (1982) and operates on the premises of the Centro Atomico Bariloche belonging to the Argentine Nuclear Authority, the CNEA. It is an open-pool reactor, designed to use 20% enriched Uranium fuel, and is moderated and cooled by light water. Figure 8 shows the measured power (from the processed outputs of the Pulse and Campbell Channels) versus the real reactor power (inferred from the reference current of the reactor control system). From the graph can be seen that the board allows the measure of the reactor power along all its range (0 to 5x10' watts) with a maximum full scale error less than 1%. The switching between channels in the suitable point allows to keep low the value of the power calculation error by discarding the low accuracy data zones. The neutron flux measurements (not seen in the figure) showed a Campbell Channel operative range from lO'' to 10^° nv and a Pulse Channel operative range from 10° to 10* nv.
10"' 10" 10' lO'^ 10-^ 10^ 10^
REACTOR POWER (W)
FIGURE 8. Experimental Results in RA6 Reactor. The upper limit of the Pulse Channel comes from the pile up of the pulses while the lower limit of the Campbell Channel comes from gamma activity background and thermal noise on electronic devices. The influence of gamma activity background could be diminished by the use of higher orders of Campbell and the influence of noise could be
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reduced by the use of cross correlation of the CampbeU signal. However, both improvements from the point of view of the extension of the overlapping region, requires a more complex electronics and with this an increase in the number of failure modes of all the system. An almost two decades width overlapping region is good enough to allow a smooth transition between the two neutron flux measurement processes (pulse count rate and fluctuation signal variance). To prevent from erratic switching between both channels because of the statistical uncertainty of the measurement, a hysteresis behavior is provided around the switching point.
The switching decision depends on the value of the Campbell Channel output. The use of the Pulse Channel output value, although better from the point of view of the statistical uncertainty of the measurement, results unreliable. This is because at high neutron flux, its behavior becomes ambiguous and repeats the characteristic values of lower flux but with decreasing tendency.
Also, as the WRND output has to reflect the flux changes with minimum delays but without increasing too much the statistical uncertainty, a sampling period of 5 ms was chosen. In the case of the Pulse Channel a measurement period of that length produces an unacceptable fluctuation of the output for low count rates. In order to overcome this problem, a control mechanism has been provided to change the length of the counting period from 4 ms to 1 s in steps of 4 ms to keep the statistical uncertainty at a minimum.
SPACE ENVIRONMENT TOLERANT DESIGN
Although, in this phase of the development the board has been implemented using COTS parts, all of them have been carefully selected to have equivalent versions that fulfill radiation tolerance, high reliability and extended-range temperature characteristics. The board has been ruggedized in order to resist the impact of any stress coming from spacecraft acceleration. Any possible failure of the system has been mitigated at system level by using (see fig. 2) triple redundancy. Reliability has been enhanced by significantly reducing the number of electronics parts on the board. Most of the functions on the board are digital and all digital mechanisms are included inside two rad tolerant antifuse technology FPGAs (see fig. 5). SEU and SEFI radiation effects are mitigated by using hard-wired TMR flipflops for internal registers. The software for the communication and processing sections runs directly from internal ROMs and both processors uses Watch Dog Timers to fulfill availability requirements.
CONCLUSIONS
A Wide Range Neutron Detector system has been upgraded, according to specifications on WRND NASA SBIR Phase II Report (Merk, 2005), with the digital processing of its signals. The digitalization of these processes allowed a high integration of this part of the electronics, increasing in this way its reliability. Although the DSP board is at the prototype stage of its development, several design considerations has been done in order to produce a design that will allow the flight model to fulfill space mission requirements, such as component selection and technology independent code design.
NOMENCLATURE
ADC CNEA COTS DAC DSP FPGA IEEE INTI LOG MHz OPAL RAM
= Analog to Digital Converter = Comision Nacional de Energia Atomica = Commercial off the shelf = Digital to Analog Converter = Digital Signal Processor = Field Programmable Gate Array = Institute of Electronic and Electrical Engineers = Instituto Nacional de Tecnologia Industrial = Logarithmic scale neutron flux = Megahertz = Open Pool Advanced Light-Water Reactor = Random Access Memory
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RATE = Rate value of the LOG signal
RTL = Register Transfer Level
SBC = Single Board Computer
SEFI = Single Event Functional Interrupt
SEU = Single Event Upset
SOC = System On Chip
UF
= Uncertainty Factor
UART = Universal Asynchronous Receiver Transmitter
VHDL = VHSIC Hardware Description Language
VHSIC = Very High Speed Integrated Circuit
VME = Versa Module Eurocard
WB = Wishbone bus
WRND = Wide Range Neutron Detector
ACKNOWLEDGMENTS
Thanks are due to John Merk and to Payload System staff for the first tests of the DSP board. We also want to acknowledge to Carlos Diaz, Ricardo Germi and Rodolfo Modgan for the operation of the CNEA Research Reactor RA6 and to Eduardo Nassif for his help in the evaluation of the results.
REFERENCES
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